Means for dividing the frequency of an input signal by an even number are generally known. Using these means, a desired 50% pulse ratio can be achieved i.e. where the output signal is "high" fifty percent of the time and low 50% of the time i.e. giving a unity mark-space ratio.
Dividing frequencies by an odd number is also known and various means of such division exist, however, all the means of the prior art are encumbered with the restriction that the pulse ratio of the output signal is not 50% but remains less than 50%.
If the ratio R between the input clock frequency and the output clock frequency is relatively low i.e. less than 11 to 15, a programmable counter with a pulse ratio of 1/R can be used when the input clock frequency is less than 10 MHz. If the ratio R is high, the input clock frequency must be relatively low, 1 to 2 MHz at most. In both instances the pulse ratio is 1/R unless additional decoding logic is used.
When the ratio R is high, several consecutive counters may be used. If the counters act synchronously, the pulse ratio is always 1/R. The desired frequency can also be generated by adding a completely new frequency into the system, but an extra local oscillator is required in such instance.
Another problem has been that, to date, it has been difficult to have the output signal synchronized. In order to exclude any phase jitter or other distortions, the leading edges should be evenly spaced, as should also the trailing edges. No generally known appropriate means exist for this purpose.
Division by an odd number has, therefore generally been abandoned, and a great number of oscillators of different frequencies have been adopted. This involves extra component costs.
According to the present invention, there is provided a divider comprising, means operable to divide the frequency of an input signal by a pre-determined even integer and to supply the divided signal as an output, and means operable to add one cycle to the divided output signal to provide an output signal for the divider whereby the divider output signal has a frequency which is equal to the frequency of the input signal divided by a pre-determined odd integer. This has the advantage that, whereas previously no appropriate means for arbitrarily forming the pulse ratio of a signal have been generally known, by generalizing the principle of dividing with odd numbers, a systematic and clear-cut means has been provided for the said purpose.
The divider of the present invention provides frequency division by means of a 2N+1 counter where N is the number of flip-flops in the divider, in which the pulse ratio at high N values approaches 50%. Thus because a pulse ratio of almost 50% can be formed with the counter, the output of the circuit can be used for clock frequencies of large circuits both on the leading and the trailing edge. In this case, no problems are caused by deviations between the leading edges and trailing edges.
The outgoing wave form almost approaches symmetry. The counter is completely synchronous. With the present invention, the clock frequency of the system is obtained from the input clock frequency when the ratio R between the input clock frequency and the output clock frequency is an odd integer. It was possible earlier, with the aid of a programmable synchronous counter, to produce the same input signal and output signal ratio, but the pulse ratio has not been close to 50%, especially in high ratios. If the ratio R is an even integer, the output of the counter to be programmed can always be divided with two so that the pulse ratio remains the same.
The invention will now be described by way of example only, with reference to the accompanying figures, of which: